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发表于 2016-5-1 03:00:47
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R2R方第三位选手是
SCHIIT YGGDRASIL (21,500元)
技术特点:采用4片AD5791芯片组成的21bit全平衡R2R结构,Adapticlock时钟系统确保极低Jitter,支持USB3.0输入,Schiit自行开发的数字滤波,以及插板式升级功能。
Inputs: AES/EBU XLR, RCA SPDIF, BNC SPDIF, Optical SPDIF, USB
Input Capability: up to 24/192 for all inputs
Input Receiver, SPDIF: AKM AK4113
Input Receiver, USB: C-Media CM6632
Clock Management: Bitperfect clock management at all native sample rates via Adapticlock analysis and VCXO/VCO regeneration, plus asynchronous USB Gen 3 module
Digital Filter: proprietary Schiit bitperfect closed-form digital filter implemented on Analog Devices SHARC DSP processor
D/A Conversion IC: Analog Devices AD5791BRUZ x 4 (2 per channel, hardware balanced configuration)
Analog Stages: Fully discrete JFET buffers for balanced output and discrete JFET summing stages for single-ended output, direct coupled throughout
Output: One pair XLR balanced and two pairs RCA single-ended
Output Impedance: 75 ohms
Frequency Response, Analog Stage: 20Hz-20Khz, +/-0.1dB, 0.5Hz-200KHz, -1dB
Maximum Output: 4.0V RMS (balanced), 2.0V RMS (single-ended)
THD: Less than 0.006%, 20Hz-20KHz, at full output
IMD: <0.007%, CCIF, at full output
SNR: > 117dB, referenced to 2V RMS
Power Supply: two transformers (one for digital supplies, one for analog supplies) plus one input choke for discrete, dual mono, shunt-regulated analog +/-24V supply, plus 12 separate local regulated supplies for DACs and digital sections, including high-precision, low-noise LM723 regulation in critical areas.
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